A. Field of the Invention
The present invention relates generally to semiconductor manufacturing and semiconductor devices and, more particularly, to static random access memories (SRAMs).
B. Description of Related Art
SRAM is random access memory that retains its stored data as long as power is supplied to the SRAM cells. Unlike dynamic RAM (DRAM), which stores bits in cells consisting of a capacitor and a transistor, SRAM does not have to be periodically refreshed. SRAM generally provides faster memory bit access than DRAM.
One conventional SRAM cell include six transistors arranged as cross-coupled inverters to form a flip-flop. Other conventional SRAM cells include a single transistor and two tunnel diodes. The single transistor in this SRAM may be a MOSFET type transistor.
Conventional MOSFETs have difficulty scaling below 50 nm fabrication processing. To develop sub-50 nm MOSFETs, double-gate MOSFETs have been proposed. In several respects, the double-gate MOSFETs offer better characteristics than the conventional bulk silicon MOSFETs. These improvements arise because the double-gate MOSFET has a gate electrode on both sides of the channel, rather than only on one side as in conventional MOSFETs. When there are two gates, the electric field generated by the drain is better screened from the source end of the channel. Also, two gates can control roughly twice as much current as a single gate, resulting in a stronger switching signal.
It would be desirable to more efficiently implement an SRAM cell, as this would increase the overall efficiency of the semiconductor memory devices.
Implementations consistent with the present invention include an SRAM cell using a single FinFET transistor and two tunnel diodes formed from FinFET fins.
One aspect of the invention is directed to an SRAM cell that includes a FinFET that has multiple channel regions each formed by a separate fin of the FinFET. The SRAM cell further includes a memory node connected to the FinFET and first and second resonant tunnel diodes. The first resonant tunnel diode has two terminals, one of the two terminals being connected to the memory node. The second resonant tunnel diode has two terminals, one of the two terminals being connected to the memory node.
A second aspect of the invention is directed to an SRAM cell that includes a switch, a memory node, and first and second resonant tunnel diodes. The first and second resonant tunnel diodes have two terminals. One of the two terminals of each resonant tunnel diode is connected to the memory node. The first and second resonant diodes are formed from an undoped fin surrounded by a dielectric layer.